A dividing ratio changeable digital PLL based on phase state memory and double clock-edge detection

被引：2

作者：

Fujimoto, Kuniaki ^{[1
]}

Sasaki, Hirofumi ^{[1
]}

Yahara, Mitsutoshi ^{[2
]}

机构：

[1] School of Engineering, Kyushu Tokai University, Kumamoto-shi, Kumamoto 862-8652

[2] Tokai University, Fukuoka Junior College, Munakata-shi, Fukuoka 811-4198

来源：

IEEJ Transactions on Electronics, Information and Systems | 2008年 / 128卷 / 07期

关键词：

Digital phase locked loop; Jitter; Lock-in range; Pull-in time;

D O I：

10.1541/ieejeiss.128.1185

中图分类号：

学科分类号：

摘要：

In this paper, we propose the dividing ratio changeable digital phase locked loop (PLL) based on phase state memory and double clock-edge detection in which satisfies three characteristics of a low jitter, wide lock-in range, and fast pull-in at the same time. The counter for the double edge detection of the base clock reduces the circuit scale by using the selector. In a steady state, the output jitter of the proposed digital PLL becomes always half pulse width of the base clock regardless of the frequency fluctuation of the base clock. Also, the upper bound frequency of the lock-in range becomes 6 times that of the conventional dividing ratio changeable digital PLL, when the permissible output jitter is identical. Furthermore, the fast pull-in is finishes in one period of the input signal and the pulse width of the multiplication output signal becomes almost constant. © 2008 The Institute of Electrical Engineers of Japan.

引用

页码：24+1185 / 1190

共 5 条

[1]

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[2]

Hsu T.Y., Shieh B.J., Lee C.Y., An all-digital phase-locked loop (ADPLL)-based clock recovery circuit, IEEE J. Solid-State Circuits, 34, 8, (1999)

[3]

Watanabe T., Yamauchi S., An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time, IEEE J. Solid-State Circuits, 38, 2, pp. 198-204, (2003)

[4]

Sasaki H., Yahara M., Fujimoto K., Sasaki H., A low jitter in multiple frequency of dividing ratio changeable type ADPLL, ITC-CSCC2002, Proceedings, 3, pp. 1630-1633, (2002)

[5]

Sasaki H., Yahara M., Fujimoto K., A new DCPLL with low jitter based on double-edge mode, IEEE TENCON 2004, Proceedings, C, (2004)

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