High-performance CMOS variability in the 65-nm regime and beyond

被引：0
|
作者：
Bernstein, Kerry [1 ]
Frank, David J. [1 ]
Gattiker, Anne E. [2 ]
Haensch, Wilfried [1 ]
Ji, Brian L. [1 ]
Nassif, Sani R. [2 ]
Nowak, Edward J. [3 ]
Pearson, Dale J. [1 ]
Rohrer, Norman J. [3 ]
机构：
[1] IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, United States
[2] IBM Research Division, Austin Research Laboratory, 11501 Burnet Road, Austin, TX 78758, United States
[3] IBM Systems and Technology Group, 1000 River Street, Essex Junction, VT 05452, United States
来源：
IBM Journal of Research and Development | 2006年 / 50卷 / 4-5期
关键词：
45;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
Journal article (JA)
引用
收藏
页码：433 / 449
相关论文
共 50 条
  • [31] A Multiband Terahertz Detector in 65-nm CMOS for Spectroscopic Imaging
    Liu, Zhao-Yang
    Qi, Feng
    Wang, Ye-Long
    Liu, Peng-Xiang
    Li, Wei-Fan
    IEEE TRANSACTIONS ON TERAHERTZ SCIENCE AND TECHNOLOGY, 2024, 14 (06) : 781 - 790
  • [32] Towards an Improved Model for 65-nm CMOS at Cryogenic Temperatures
    Ning, Jie
    Schormans, Matthew
    Demosthenous, Andreas
    2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2020,
  • [33] Analysis and Design of High Performance Wireless Power Delivery Using On-chip Octagonal Inductor in 65-nm CMOS
    Mao, Weijun
    Sun, Liusheng
    Xu, Junwei
    Wu, Jiajia
    Zhu, Xiaolei
    2015 28TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC), 2015, : 401 - 405
  • [34] High-performance on-chip interconnect circuit technologies for sub-65nm CMOS
    Kaul, H
    IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2005, : 324 - 324
  • [35] Embedded FeRAM Challenges in the 65-nm Technology Node and Beyond
    Kato, Yoshihisa
    Tanaka, Hiroyuki
    Isogai, Kazunori
    Kaibara, Kazuhiro
    Kaneko, Yukihiro
    Shimada, Yasuhiro
    Brubaker, Matt
    Celinska, Jolanta
    McMillan, Larry D.
    de Araujo, Carlos. A. Paz
    2006 15TH IEEE INTERNATIONAL SYMPOSIUM ON APPLICATIONS OF FERROELECTRICS, 2007, : 78 - +
  • [36] Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology
    Bae, Woorham
    Jeong, Gyu-Seob
    Kim, Yoonsoo
    Chi, Han-Kyu
    Jeong, Deog-Kyoon
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 24 (06) : 2234 - 2243
  • [37] Compact Modeling and simulation of circuit reliability for 65-nm CMOS technology
    Wang, Wenping
    Reddy, Vijay
    Krishnan, Anand T.
    Vattikonda, Rakesh
    Krishnan, Srikanth
    Cao, Yu
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2007, 7 (04) : 509 - 517
  • [38] A High-Voltage UWB Pulse Generator Using Passive Amplification in 65-nm CMOS
    Gao, Shengkai
    Moez, Kambiz
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2020, 67 (12) : 5530 - 5539
  • [39] An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology
    Chen, Qingyu
    Wang, Haibin
    Chen, Li
    Li, Lixiang
    Zhao, Xing
    Liu, Rui
    Chen, Mo
    Li, Xuantian
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2016, 32 (03): : 385 - 391
  • [40] A 14-91 GHz Distributed Amplifier in 65-nm CMOS
    Hsu, Ching-Min
    Wang, Yunshan
    Wang, Huei
    2020 IEEE ASIA-PACIFIC MICROWAVE CONFERENCE (APMC), 2020, : 1009 - 1011
12345