Enhancing Reliability and Energy Efficiency in Many-Core Processors Through Fault-Tolerant Network-on-Chip

This article presents a proposal for fault-tolerant task mapping on many-core processors to enhance system performance and reduce communication energy. The proposed algorithm maps tasks onto a 2-D mesh network-on-chip (NoC) and a modified NoC (MNoC) platform. The focus of this article is primarily on addressing permanent faults. In the scenario of a permanent fault within the mapped core, the algorithm also proposes a spare core placement strategy. This involves allocating the spare core based on considerations related to communication energy. The proposed task mapping algorithm underwent evaluation using various benchmarks, including multimedia and synthetic benchmarks. The results were then compared to those obtained from a 2-D mesh NoC and three related algorithms, all under the same task graph and NoC size. The simulation results showed that the proposed mapping algorithm on the modified NoC platform leads to improved performance and communication energy reductions when compared to the 2-D mesh NoC and the other three algorithms. To validate the proposed fault-tolerant task mapping algorithm on the modified NoC platform, A Field Programmable Gate Array (FPGA) was used to measure performance metrics such as application runtime, area, and on-chip power consumption in both faulty and non-faulty conditions. The hardware results indicated significant improvements when comparing the proposed FTTM on MNoC and 2-D NoC with existing approaches.