A fault-tolerant design of faults and congestion-aware router in Three-dimensional Network-on-Chip

被引：0
|
作者：
机构：
[1] Ouyang, Yi-Ming
[2] Zhang, Yi-Dong
[3] Liang, Hua-Guo
[4] Huang, Zheng-Feng
来源：
Ouyang, Y.-M. (oyymbox@163.com) | 1600年 / Chinese Institute of Electronics卷 / 41期
关键词：
Network-on-chip;
D O I：
10.3969/j.issn.0372-2112.2013.05.013
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [1] Congestion-Aware Network-on-Chip Router Architecture
    Wang, Chifeng
    Hu, Wen-Hsiang
    Bagherzadeh, Nader
    15TH CSI INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS 2010), 2010, : 137 - 144
  • [2] AFTER: Asynchronous Fault-Tolerant Router Design in Network-on-Chip
    Ouyang, Yiming
    Chen, Qi
    Wang, Xiumin
    Ouyang, Xiaoye
    Liang, Huaguo
    Du, Gaoming
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2016, 25 (06)
  • [3] An Unified Online Fault-tolerant Mechanism for FIFO Faults in Network-on-Chip Router
    Xu, Linfu
    Hang, Yanxi
    Guo, Pengfei
    Dai, Qiang
    2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2016, : 1419 - 1421
  • [4] Scalable load balancing congestion-aware Network-on-Chip router architecture
    Wang, Chifeng
    Hu, Wen-Hsiang
    Bagherzadeh, Nader
    JOURNAL OF COMPUTER AND SYSTEM SCIENCES, 2013, 79 (04) : 421 - 439
  • [5] A congestion-aware OE router employing fair arbitration for network-on-chip
    Lu Liu
    Yadong Sun
    Zhangming Zhu
    Yintang Yang
    Journal of Semiconductors, 2018, (12) : 196 - 202
  • [6] A congestion-aware OE router employing fair arbitration for network-on-chip
    Liu, Lu
    Sun, Yadong
    Zhu, Zhangming
    Yang, Yintang
    JOURNAL OF SEMICONDUCTORS, 2018, 39 (12)
  • [7] A congestion-aware OE router employing fair arbitration for network-on-chip
    Lu Liu
    Yadong Sun
    Zhangming Zhu
    Yintang Yang
    Journal of Semiconductors, 2018, 39 (12) : 196 - 202
  • [8] Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router
    Melo, Douglas Rossi
    Zeferino, Cesar Albenes
    Bezerra, Eduardo Augusto
    Dilillo, Luigi
    2021 16TH INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA (DTIS 2021), 2021,
  • [9] Designing fault-tolerant network-on-chip router architecture
    Eghbal, Ashkan
    Yaghini, Pooria M.
    Pedram, H.
    Zarandi, H. R.
    INTERNATIONAL JOURNAL OF ELECTRONICS, 2010, 97 (10) : 1181 - 1192
  • [10] Design and implementation of congestion aware router for network-on-chip
    Balakrishnan, Melvin T.
    Venkatesh, T. G.
    Bhaskar, A. Vijaya
    INTEGRATION-THE VLSI JOURNAL, 2023, 88 : 43 - 57
12345