Multi-optical network-on-chip for large scale MPSoC

被引：13

作者：

Le Beux S. ^{[1
]}

Trajkovic J. ^{[1
]}

O'Connor I. ^{[2
]}

Nicolescu G. ^{[1
]}

Bois G. ^{[1
]}

Paulin P. ^{[3
]}

机构：

[1] Département de Génie Informatique et de Génie Logiciel, École Polytechnique de Montréal, Montréal

[2] Lyon Institute of Nanotechnology (INL), École Centrale de Lyon, Ecully

[3] STMicroelectronics, Ottawa

来源：

IEEE Embedded Systems Letters | 2010年 / 2卷 / 03期

关键词：

Design methodology; optical network-on-chip (ONoC);

D O I：

10.1109/LES.2010.2057407

中图分类号：

学科分类号：

摘要：

Optical network-on-chip (ONoC) architectures are emerging as promising contenders to solve bandwidth and latency issues in multiprocessor systems-on-chip (MPSoC). However, current on-chip integration technologies for optical interconnect allow interconnecting only dozens of IPs. Scaling with MPSoCs composed of hundreds of IPs thus, relies on unpredictable technological innovations. In this letter, we propose a method that combines multiple ONoCs. Each ONoC is small enough to rely on already existing and proven technologies. We evaluate the approach for various interconnect scenarios, showing that it scales well with the size of the MPSoC architectures. © 2010 IEEE.

引用

页码：77 / 80

页数：3

共 13 条

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