Optimization scheme for mid-bond test time on 3D-stacked ICs

被引:0
|
作者
Chang, Hao [1 ,3 ]
Liang, Hua-Guo [2 ]
Jiang, Cui-Yun [4 ]
Ouyang, Yi-Ming [1 ]
Xu, Hui [1 ]
机构
[1] School of Computer and Information, Hefei University of Technology, Hefei,Anhui,230009, China
[2] School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei,Anhui,230009, China
[3] School of Management Science and Engineering, Anhui University of Finance and Economics, Bengbu,Anhui,233030, China
[4] School of Mathematics, Hefei University of Technology, Hefei,Anhui,230009, China
来源
Tien Tzu Hsueh Pao/Acta Electronica Sinica | 2015年 / 43卷 / 02期
关键词
Electric power utilization;
D O I
10.3969/j.issn.0372-2112.2015.02.029
中图分类号
学科分类号
摘要
Mid-bond test can detect the defects introduced in the bonding process earlier, which will also result in the significant growth of the test application time and test power consumption. Considering the test TSVs, test pins and power consumption, Integer Linear Programming was used to optimize the test application time under three stack structures. Different from the post bond test, compared with the Pyramid structure, the test application time decreases by 4.39% and 40.72%, the number of test TSV increases by 11.84% and 52.24%, the number of test pin reduces by 10.87% and 7.25% in the diamond structure and the inverted Pyramid structure respectively. Considering the test power consumption, the test application time increases by 10.07% in the Pyramid structure, while the diamond structure and the inverted Pyramid structure only increase by 4.34% and 2.65%. The experimental results show that the diamond structure and the inverted Pyramid structure have greater advantage over the Pyramid structure in the mid-bond test. ©, 2015, Chinese Institute of Electronics. All right reserved.
引用
收藏
页码:393 / 398
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