Optimization of Multi-Fins FinFET Implemented on SOI Wafer Based on SiGe and Gaussian Process Regression

被引:0
作者
Yalung, Christofer N. [1 ]
Yamwong, Wittawat [2 ]
Tantraviwat, Doldet [3 ,4 ]
机构
[1] Chiang Mai Univ, Fac Sci, Philosophy Program Nanosci & Nanotechnol, Mat Sci Res Ctr,Int Program Interdisciplinary, Chiang Mai 50200, Thailand
[2] Natl Elect & Comp Technol Ctr NECTEC, Thai Microelect Ctr TMEC, Chachoengsao 24000, Thailand
[3] Chiang Mai Univ, Fac Engn, Dept Elect Engn, Chiang Mai 50200, Thailand
[4] Chiang Mai Univ, Fac Sci, Ctr Excellence Mat Sci & Technol, Chiang Mai 50200, Thailand
来源
IEEE ACCESS | 2024年 / 12卷
关键词
FinFETs; Silicon; Germanium; Optimization; Silicon germanium; Mathematical models; Support vector machines; Artificial neural networks; Logic gates; Predictive models; Gaussian processes; Machine learning; Tri-gate FinFET; multi-fins FinFET; optimization; SiGe mole fraction; surrogate optimization; Gaussian process regression; propagation delay; machine learning; DEVICE; PERFORMANCE; DESIGN; NUMBER; IMPACT;
D O I
10.1109/ACCESS.2024.3489727
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Despite advancements in mitigating the short channel effect using high-k materials, multi-gate structures, and silicon-germanium (SiGe) alloys in three-dimensional FinFETs, performance trade-offs remain. This study introduces a novel machine learning framework utilizing a Gaussian process regression model (GPRM) and surrogate optimization (SO) to optimize design parameters of n-type and p-type SiGeFinFETs. With this approach targeting switching ratio (SR), the optimal mole fractions of the n-type FinFET are Si0.7Ge0.3 for source extension (S-ext), Si0.2Ge0.8 for channel (L-g), and Si for drain extension (D-ext),achieving an SR of 6.9x10(9). For p-type FinFET, the optimal configuration is Si0.9Ge0.1 for Sext, and Si for L-g and D-ext with an SR of 5.81x10(7). The optimization of n-type and p-type multi-fin FinFETs(NmFinFET and PmFinFET) was also investigated, considering varied input parameters such as L-g, fin height(F-h), fin width (F-w), S-ext, D-ext, and the number of fins (numfin). The optimized devices for NmFinFET and PmFinFET, prioritizing speed, have the same dimensions: L-g = 10 nm, F-h = 42 nm,F-w = 10 nm, S-ext = 3 nm, D-ext = 4 nm, and numfin = 5. An inverter constructed using these optimized parameters showed a simulated propagation delay of 2 ps. This machine learning-driven approach demonstrates remarkable effectiveness in optimizing FinFET designs. The framework's ability to simultaneously optimize multiple objectives showcases its potential for advancing semiconductor device engineering.
引用
收藏
页码:163444 / 163451
页数:8
相关论文
共 32 条
  • [1] [Anonymous], 2015, SENTAURUS DEVICE USE
  • [2] [Anonymous], 2014, Three-dimensional Simulations of 7 nm Silicon Germanium FinFETs Using Monte Carlo Model and Drift-Diffusion Model With Ballistic Mobility, P1
  • [3] [Anonymous], 2017, SentaurusDevice User Guide
  • [4] Optimization of Dual-K Gate Dielectric and Dual Gate Heterojunction SOI FinFET at 14 nm Gate Length
    Aujla, Samjot Kaur
    Kaur, Navneet
    [J]. IETE JOURNAL OF RESEARCH, 2022, 68 (01) : 658 - 666
  • [5] Auth C., 2012, 2012 IEEE Symposium on VLSI Technology, P131, DOI 10.1109/VLSIT.2012.6242496
  • [6] Bae DI, 2016, INT EL DEVICES MEET
  • [7] An optimized junctionless GAA MOSFET design based on multi-objective computation for high-performance ultra-low power devices
    Bendib, T.
    Djeffal, F.
    Meguellati, M.
    [J]. JOURNAL OF SEMICONDUCTORS, 2014, 35 (07)
  • [8] Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure
    Boukortt, Nour El I.
    Lenka, Trupti Ranjan
    Patane, Salvatore
    Crupi, Giovanni
    [J]. ELECTRONICS, 2022, 11 (01)
  • [9] Multiple-gate SOI MOSFETs
    Colinge, JP
    [J]. SOLID-STATE ELECTRONICS, 2004, 48 (06) : 897 - 905
  • [10] Compact Model of Drain Current in Short-Channel Triple-Gate FinFETs
    Fasarakis, Nikolaos
    Tsormpatzoglou, Andreas
    Tassis, Dimitrios H.
    Pappas, Ilias
    Papathanasiou, Konstantinos
    Bucher, Matthias
    Ghibaudo, Gerard
    Dimitriadis, Charalabos A.
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (07) : 1891 - 1898