Dynamic and static power co-analysis of CMOS circuits

被引：0
|
作者：
Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080, China [1 ]
不详 [2 ]
不详 [3 ]
机构：
来源：
Jisuanji Gongcheng | 2006年 / 10卷 / 231-233期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
An analysis method of real power estimation is proposed to achieve the co-analysis of dynamic and leakage power. This paper defines two parameters of variation and expectation rate (VER) and maximum-skew ratio (MSR) along with expectation and variation to describe the complicated behavioral of power, which offer more valuable information for low power design. Experiments with some of ISCAS85, ISCAS89 and ITC99 benchmark circuits show the analysis method and the proposed parameters are very useful for low power design and energy delivery.
引用
收藏
相关论文
共 50 条
  • [21] Power Consumption Analysis in Static CMOS Gates
    Wiltgen, Alberto, Jr.
    Escobar, Kim A.
    Reis, Andre, I
    Ribas, Renato P.
    2013 26TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN (SBCCI 2013), 2013,
  • [22] Dynamic circuits for CMOS and BiCMOS low power VLSI design
    Zhu, Z
    Carlson, BS
    ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 4, 1996, : 197 - 200
  • [23] Low power arithmetic circuits in feedthrough dynamic CMOS logic
    Navarro-Botello, Victor
    Montiel-Nelson, Juan A.
    Nooshabadi, Saeid
    Dyer, Mike
    IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS,, 2006, : 709 - +
  • [24] Delay Optimization Considering Power Saving in Dynamic CMOS Circuits
    Yelamarthi, Kumar
    Chen, Chien-In Henry
    2011 12TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), 2011, : 364 - 369
  • [25] Synthesis of high performance low power dynamic CMOS circuits
    Samanta, D
    Sinha, N
    Pal, A
    ASP-DAC/VLSI DESIGN 2002: 7TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE AND 15TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2002, : 99 - 104
  • [26] Univariate Power Analysis Attacks Exploiting Static Dissipation of Nanometer CMOS VLSI Circuits for Cryptographic Applications
    Bellizia, Davide
    Bongiovanni, Simone
    Monsurro, Pietro
    Scotti, Giuseppe
    Trifiletti, Alessandro
    IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, 2017, 5 (03) : 329 - 339
  • [27] Fault diagnosis for static CMOS circuits
    Wen, XQ
    Tamamoto, H
    Saluja, KK
    Kinoshita, K
    SIXTH ASIAN TEST SYMPOSIUM (ATS'97), PROCEEDINGS, 1997, : 282 - 287
  • [28] Trading off static power and dynamic performance in CMOS digital circuits: bulk versus double gate SOI MOSFETs
    Agostinelli, M.
    Alioto, M.
    Esseni, D.
    Selmi, L.
    ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2007, : 191 - +
  • [29] Static power reduction in nano CMOS circuits a through an adequate circuit synthesis
    Jozwiak, L.
    Gawlowski, D.
    Slusarczyk, A.
    Chojnacki, A.
    MIXDES 2007: PROCEEDINGS OF THE 14TH INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS:, 2007, : 172 - 177
  • [30] System level optimization of static power consumption in nano-CMOS circuits
    Helms, D.
    MIXDES 2007: Proceedings of the 14th International Conference on Mixed Design of Integrated Circuits and Systems:, 2007, : 169 - 171
12345