Photolithography process simulation for integrated circuits and microelectromechanical system fabrication

被引：0
|
作者：
Key Laboratory of MEMS, Southeast University, Nanjing 210096, China [1 ]
机构：
来源：
Pan Tao Ti Hsueh Pao | 2006年 / 4卷 / 705-711期
关键词：
Photolithography;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [21] Fabrication process of planarized multi-layer Nb integrated circuits
    Satoh, T
    Hinode, K
    Akaike, H
    Nagasawa, S
    Kitagawa, Y
    Hidaka, M
    IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2005, 15 (02) : 78 - 81
  • [22] RESISTLESS FABRICATION OF INTEGRATED CIRCUITS
    OKEEFFE, TW
    HANDY, RM
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1968, ED15 (06) : 436 - &
  • [23] Microelectromechanical probe for an integrated electroantennographic system
    Ghodsian, B
    Syrzycki, M
    Gries, G
    Parameswaran, M
    EIGHTH ANNUAL IEEE INTERNATIONAL CONFERENCE ON INNOVATIVE SYSTEMS IN SILICON, 1996 PROCEEDINGS, 1996, : 89 - 97
  • [24] Monolithic integration fabrication process of thermoelectric and vibrational devices for microelectromechanical system power generator
    Sato, Norio
    Kuwabara, Kei
    Ono, Kazuyoshi
    Sakata, Tomomi
    Morimura, Hiroki
    Terada, Jun
    Kudou, Kazuhisa
    Kamei, Toshikazu
    Yano, Masaki
    Machida, Katsuyuki
    Ishii, Hiromu
    Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 2007, 46 (9 A): : 6062 - 6067
  • [25] Monolithic integration fabrication process of thermoelectric and vibrational devices for microelectromechanical system power generator
    Sato, Norio
    Kuwabara, Kei
    Ono, Kazuyoshi
    Sakata, Tomomi
    Morimura, Hiroki
    Terada, Jun
    Kudou, Kazuhisa
    Kamei, Toshikazu
    Yano, Masaki
    Machida, Katsuyuki
    Ishii, Hiromu
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2007, 46 (9A): : 6062 - 6067
  • [26] Fabrication of stacked logic circuits for printed integrated circuits
    Kudo, Kazuhiro
    Kodera, Isao
    Aino, Rui
    Yamauchi, Hiroshi
    Kuniyoshi, Shigekazu
    Sakai, Masatoshi
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2014, 53 (05)
  • [27] A new open hole buried heterostructure process for the fabrication of photonic integrated circuits
    Sun, Y
    Ji, XM
    Chen, Z
    Yan, JZ
    Cal, JX
    Raj, M
    Choa, FS
    2003 IEEE LEOS ANNUAL MEETING CONFERENCE PROCEEDINGS, VOLS 1 AND 2, 2003, : 1028 - 1029
  • [28] FABRICATION OF INTEGRATED CIRCUITS USING ELECTRON IMAGE PROJECTION SYSTEM (ELIPS)
    OKEEFFE, TW
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1970, ED17 (06) : 465 - &
  • [29] Demonstration of 50-mV Digital Integrated Circuits with Microelectromechanical Relays
    Ye, Z. A.
    Almeida, S.
    Rusch, M.
    Perlas, A.
    Zhang, W.
    Sikder, U.
    Jeon, J.
    Stojanovic, V.
    Liu, T. -J. K.
    2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2018,
  • [30] SILICON INTEGRATED CIRCUIT FABRICATION PROCESS MODELLING AND SIMULATION.
    Tarnay, Kalman
    Mizsei, Janos
    Masszi, Ferenc
    Baji, Pal
    Kovacs, Balazs
    Rang, Toomas
    Drozdy, Gyozo
    Periodica Polytechnica Electrical Engineering, 1980, 24 (1-2): : 109 - 113
12345