A decoding algorithm based on layered decoding and min-max for nonbinary LDPC codes

被引:0
作者
机构
[1] School of Electronic Information Engineering, Tianjin University
来源
Yang, W. (yangkk3@tju.edu.cn) | 1677年 / Science Press卷 / 35期
关键词
Layered decoding; Min-max; NonBinary Low-Density Parity-Check (NB-LDPC) codes; Quasi-cyclic codes;
D O I
10.3724/SP.J.1146.2012.01634
中图分类号
学科分类号
摘要
Based on decoding algorithms available nowadays, a high efficiency decoding algorithm for nonbinary low-density parity-check codes is proposed. The algorithm takes advantage of both the layered decoding algorithm and the Min-max algorithm, which not only achieves the low complexity and the low memory requirement, but also speeds up the decoding by two times. Simulations for a (620,509) code over GF(25) show that with the same bit error rate, the maximum iteration times of the proposed algorithm required is just 45% of Zhang's algorithm presented in 2011.
引用
收藏
页码:1677 / 1681
页数:4
相关论文
共 16 条
  • [1] Gallager R.G., Low-density parity-check codes, IRE Transactions on Information Theory, 8, 1, pp. 21-28, (1962)
  • [2] Davey M.C., Mackay D., Low-density parity-check codes over GF(q), IEEE Communications Letters, 2, 6, pp. 165-167, (1998)
  • [3] Barnault L., Declercq D., Fast decoding algorithm for LDPC over GF(2q), IEEE Information Theory Workshop, pp. 70-73, (2003)
  • [4] Wymeersch H., Steendam H., Moeneclaey M., Log-domain decoding of LDPC codes over GF(q), IEEE International Conference on Communications, pp. 772-776, (2004)
  • [5] Spagnol C., Popovici E., Marnane W., Hardware implementation of GF(2m) LDPC decoders, IEEE Transactions on Circuits and Systems I: Regular Papers, 56, 12, pp. 2609-2620, (2009)
  • [6] Declercq D., Fossorier M., Decoding algorithms for nonbinary LDPC codes over GF(q), IEEE Transactions on Communications, 55, 4, pp. 633-643, (2007)
  • [7] Savin V., Min-Max decoding for non binary LDPC codes, IEEE International Symposium on Information Theory, pp. 960-964, (2008)
  • [8] Zhang X.M., Cai F., Reduced-memory forward-backward check node processing architecture for non-binary LDPC decodin, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems, pp. 1-4, (2011)
  • [9] Zhang X.M., Cai F., Efficient partial-parallel decoder architecture for quasi-cyclic nonbinary LDPC codes, IEEE Transactions on Circuits and Systems I: Regular Papers, 58, 2, pp. 402-414, (2011)
  • [10] Shuai Z., Jin S., Li L., Et al., Layered decoding for non-binary LDPC codes, Proceedings of 2010 IEEE International Symposium on Circuits and Systems, pp. 481-484, (2010)