Digital controlled oscillator design with novel 3 transistors XOR gate

The Digital controlled oscillator (DCO) is the core element of all digital phase locked loop (ADPLL) system. Here, we propose DCO structures with digital control, reduced hardware and low power consumption. Different DCOs are based on ring based topology having 3, 4 & 5 control bits. Number of control bits can be increased as per the requirement of output frequency range. DCOs using XOR as an inverter having NMOS and PMOS transistors in pull up and pull down switching networks are presented. Three bit DCO with NMOS control network shows frequency variations of [3.1763 - 3.5290] GHz with power consumption variations of [266.8491 - 293.6420] μW. Three bit DCO with PMOS network shows frequency variation of [1.9918 - 1.4313] GHz with power consumption variation of [46.1176 - 22.8450] μW. Four bit DCO with NMOS & PMOS control networks shows frequency variations of [3.2219 - 3.6114] GHz & [2.1328 - 1.4627] GHz respectively. Power consumption variations of [266.8491 - 294.9430] μW & [53.5188 - 22.8454] μW have been obtained for 4-bit DCO having NMOS & PMOS switch networks respectively. Finally the five bit DCO with NMOS & PMOS network shows output frequency range of [3.3050 - 3.5557] & [2.2579 - 1.4934] GHz. Power consumption of [266.8491 - 295.5983] μW & [61.3773 - 22.8453] μW have been reported with NMOS & PMOS network for 5-bit controlled DCO. Comparisons with earlier reported circuits have been made and reported design shows improvement over previous circuits.