3D NAND Memory and Its Application in Solid-State Drives: Architecture, Reliability, Flash Management Techniques, and Current Trends

被引：20
作者：
Li Y. [1 ]
机构：
[1] Western Digital
来源：
IEEE Solid-State Circuits Magazine | 2020年 / 12卷 / 04期
关键词：
Cells;
D O I：
10.1109/MSSC.2020.3021841
中图分类号：
学科分类号：
摘要：
In the past 20 years, NAND flash has un der gone dramatic scaling, with 2D NAND feature size going from 400 nm in 1998 to 15 nm in 2012 and 3D NAND increasing from 24 layers to 128 layers in just the past seven years. NAND density, expressed in terms of gigabits per square millimeter, has increased 100,000 times in the past 22 years [1]. Aside from physical scaling, NAND logical scaling has also undergone a transformation, evolving from singlelevel cell (SLC) to two bits per cell (MLC) to triplelevel cell (TLC) and now four bits per cell (QLC), which has been incorporated into many products. NAND die capacity has grown from 128 Mb in 2000 to 1.33 Tb in 2020. © 2009-2012 IEEE.
引用
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页码：56 / 65
页数：9
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