Clocking Wireline Systems: An Overview of Wireline Design Techniques

被引:8
|
作者
Casper, Bryan [1 ]
机构
[1] PHY Research Lab, Intel Labs, Hillsboro,OR, United States
来源
IEEE Solid-State Circuits Magazine | 2015年 / 7卷 / 04期
关键词
Clocks - Digital subscriber lines - Microelectronics - Digital integrated circuits - Locks (fasteners) - Timing circuits - Phase locked loops - Bandwidth - Modems - Oscillators (electronic) - Bandpass filters - Digital communication systems - DSL - Thermal noise;
D O I
10.1109/MSSC.2015.2476015
中图分类号
学科分类号
摘要
Over the last several decades, digital communications technologies combined with integrated circuit scaling trends have enabled the microelectronic industry to dramatically scale the bandwidth of high-loss networks such as DSL and Ethernet. These channel-limited applications depend on sophisticated equalization techniques to push well beyond the uncompensated bandwidth of the system. And in the last two decades, short-distance wireline links used for chip-to-chip communication applications have enjoyed equally impressive data rate scaling-from a few hundred megabits per second per lane to multigigabits per second in products with volumes in the billions of units. © 2015 IEEE.
引用
收藏
页码:32 / 41
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