FPGA implementation of multiphase DPWM generator with phase shedding for DC-DC converters

被引：0

作者：

Carswell, Michael ^{[1
]}

Qahouq, Jaber Abu ^{[1
]}

机构：

[1] Department of Electrical and Computer Engineering, University of Alabama, Tuscaloosa, 35487, AL

来源：

International Journal of Power Electronics | 2015年 / 7卷 / 3-4期

关键词：

DC-DC; Digital circuit; Digital control; Digital pulse width modulation; DPWM; FPGA; Interleave; Inverter; Multiphase; Phase dropping; Phase shedding; Power converter;

D O I：

10.1504/IJPELEC.2015.075426

中图分类号：

学科分类号：

摘要：

The advantages of digital control in power electronics have led to an increasing use of digital pulse width modulators (DPWM). A major focus has been on optimising the DPWM signals and architecture for DC-DC converters to maximise power conversion efficiency and reduce the overall footprint. This paper presents and discusses a dual edge counter-comparator based multiphase DPWM generator with phase-shedding and current sharing functionalities. Phase shedding, or phase dropping, in multiphase power converter is a method that uses turning OFF some of the power converter phases/channels as the load current becomes smaller/lighter in order to improve the lighter load efficiencies. The presented architecture is validated through simulated and experimental test results based off a FPGA implementation of the DPWM generator. © 2015 Inderscience Enterprises Ltd.

引用

页码：185 / 206

页数：21

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