A fast traffic lane detection system based on parallel processors and FPGA implementation

被引：0

作者：

Li Y.-J. ^{[1
]}

Zhang W.-C. ^{[1
]}

Wu N.-J. ^{[1
]}

机构：

[1] Institute of Semiconductors, Chinese Academy of Sciences

来源：

Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology | 2010年 / 32卷 / 12期

基金：

欧盟地平线“2020”;

关键词：

FPGA; Image processing; Parallel; RISC (reduced instruction set computer); Traffic lane detection;

D O I：

10.3724/SP.J.1146.2010.00111

中图分类号：

学科分类号：

摘要：

This paper proposes a parallel fast traffic lane detection system. The system consists of a 32 × 32 Processing Elements (PE) array and a dual RISC core subsystem. The PE array performs pixel-parallel image preprocessing and outputs edge features, the dual RISC core subsystem performs two lanes parameters detection in parallel based on edge features. In this way, every step in the detection process is in parallel and the detection rate is rapidly increased. The system is implemented with FPGA. The experiment shows that it has good robustness and can reach up to 50 fps. This meets the demand of real-time for lane departure warning system and makes an important sense for practical application.

引用

页码：2901 / 2906

页数：5

共 8 条

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