共 20 条
- [11] Marvin T., Lemieux G., Logic block clustering of large designs for channel-width constrained FPGAs, pp. 726-731, (2005)
- [12] Singh A., Parthasarathy G., Marek-Sadowska M., Efficient circuit clustering for area and power reduction in FPGAs, 7, 4, pp. 643-663, (2002)
- [13] Hu Y., Wang L., Tang P., Et al., A routability driven packing algorithm for FPGA, Journal of Computer-Aided Design & Computer Graphics, 19, 1, pp. 108-113, (2007)
- [14] Liu Y., Universal FPGA packing algorithm of timing optimization, Journal of Computer Engineering, 38, 2, pp. 245-247, (2012)
- [15] ABC: A system for sequential synthesis and verification
- [16] Cong J., Minkovich K., LUT-based FPGA technology mapping for reliability, pp. 517-522, (2010)
- [17] Betz V., Rose J., VPR: A new packing, placement and routing tool for FPGA research, pp. 213-222, (1997)
- [18] Chapman K., Jones L., SEU strategies for Virtex-5 devices
- [19] Zarandi H.R., Mathew J., Et al., SEU-mitigation placement and routing algorithms and their impact in SRAM-based FPGAs, pp. 380-385, (2007)
- [20] Pandit A., Akoglu A., Net length based routability driven packing, pp. 225-230, (2007)