Design, simulation and hardware implementation of low density parity check decoders using min-sum algorithm

被引：0

作者：

Ait Madi, Abdessalam ^{[1
]}

Mansouri, Anas ^{[2
]}

Ahaitouf, Ali ^{[1
]}

机构：

[1] Sidi Mohammed Ben Abdellah University, Faculty of Sciences and Technolgy, Signals Systems and Components Laboratory, B.P, 2202, Fez, V.N 30000, Morocco

[2] Sidi Mohammed Ben Abdellah University, National School of Applied Sciences of Fez, Signals Systems and Components Laboratory, Fez, Morocco

来源：

International Journal of Computer Science Issues | 2012年 / 9卷 / 2 2-3期

关键词：

Compendex;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

Computer hardware description languages

引用

页码：83 / 91

共 3 条

[1] A novel hardware-friendly self-adjustable offset min-sum algorithm for ISDB-S2 LDPC decoder
Fujitsu Laboratories LTD., 1-1, Kamikodanaka 4-chome, Nakahara-ku, Kawasaki, 211-8588, Japan
不详
European Signal Proces. Conf., (1394-1398):
[2] Residual Sliding Window Decoding Algorithm for Spatially-coupled Low-density Parity-check Codes
Zhou, Hua
Li, Zijie
Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology, 2024, 46 (03): : 867 - 874
[3] Modified channel-independent weighted bit flipping decoding algorithm for low-density-parity-check codes
Zhang, Gaoyuan
Zhou, Liang
Wen, Hong
IET COMMUNICATIONS, 2014, 8 (06) : 833 - 840

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