共 50 条
- [41] Sub-100 nm structures by neutral atom lithography Microelectronic Engineering, 1999, 46 (01): : 105 - 108
- [42] Hardmask technology for sub-100 nm lithographic imaging ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XX, PTS 1 AND 2, 2003, 5039 : 152 - 165
- [44] Device Considerations of Planar NAND Flash Memory for Extending towards Sub-20nm Regime 2013 5TH IEEE INTERNATIONAL MEMORY WORKSHOP (IMW), 2013, : 1 - 4
- [48] Challenges for Analog Circuits in sub-100 nm CMOS Nodes 2015 22ND INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS & SYSTEMS (MIXDES), 2015, : 161 - 164
- [49] Technology for sub-50nm DRAM and NAND flash manufacturing IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, 2005, : 333 - 336