A dataflow extraction technique for hardware/software partitioning of software binaries

Hardware-Software Partitioning is the key issue in the Codesign of embedded systems. Partitioning at the binary level makes the method suitable for dynamic on-the-fly partitioning of software onto hardware. This paper describes a technique that leverages a systematic transformation of the basic blocks of software binaries into dataflow descriptions for implementation of the partitioned software in hardware. The partitioned software binary to be transformed into hardware is identified using instruction level profiling. In this paper, a method is proposed for deriving a CDFG from the software partition to be transformed into hardware, by equating the final state attained due to execution of each basic block in the partition in terms of algebraic placeholders for the initial state in the system. Control nodes are used for representing branching and loops that lead to different basic blocks based on conditional expressions. The resulting Control-Data flow graph is scheduled[4] and converted to VHDL/Netlist for hardware synthesis. The proposed method shows that system delay and hardware resources are significantly reduced when compared to pure software and hardware implementations using benchmarks.