Simulation-based ATPG for low power testing of crosstalk delay faults in asynchronous circuits

被引：0
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作者：
机构：
[1] Jayanthy, S.
[2] Bhuvaneswari, M.C.
[3] Prabhu, M.
来源：
Jayanthy, S. (sjayanthyabi@gmail.com) | 1600年 / Inderscience Enterprises Ltd., Editorial Office, P O Box 735, Olney, Bucks., MK46 5WB, MK46 5WB, United Kingdom卷 / 48期
关键词：
Automatic test pattern generation - Crosstalk - Electric power utilization - Electron transitions - Low power electronics - Redundancy - Switching circuits;
D O I：
10.1504/IJCAT.2013.056920
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