A 10-bit high speed column-parallel ADC for CMOS image sensor

被引:0
作者
Yao, Suying [1 ]
Xu, Wenjing [1 ]
Gao, Jing [1 ]
Nie, Kaiming [1 ]
Xu, Jiangtao [1 ]
机构
[1] School of Electronic Information Engineering, Tianjin University
来源
Tianjin Daxue Xuebao (Ziran Kexue yu Gongcheng Jishu Ban)/Journal of Tianjin University Science and Technology | 2014年 / 47卷 / 03期
关键词
CMOS image sensor; Column-parallel ADC; Single-slope ADC; Successive-approximation ADC;
D O I
10.11784/tdxbz201205014
中图分类号
学科分类号
摘要
A column-parallel ADC for high speed and small pixel size CMOS image sensor is proposed. The proposed ADC not only improves speed but also decreases chip area by combining single-slope ADC (SS ADC) with successiveapproximation ADC (SA ADC). SS ADC converts the upper five bits, and SA ADC converts the lower five bits. The coupling capacitor of 5-bit segmented capacitive DAC in SA ADC is a unit capacitor. In addition, error correction is realized by interval overlap. The proposed ADC, which is designed in 0.18, μm 1P4M standard CMOS process, shows an effective bit number of 9.81 at 167, kHz/s. It dissipates 0.132, mW with a 3.3, V power supply. The speed is 22, times faster than that of the conventional SS ADC.
引用
收藏
页码:243 / 248
页数:5
相关论文
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