Boosting non-volatile memory performance with exhalative annealing: A novel approach to low-temperature crystallization of hafnia based ferroelectric

被引:0
|
作者
Lee, Yunseong [1 ,2 ]
Kim, Un Jeong [3 ]
Kim, Kihong [1 ]
Yun, Dong-Jin [4 ]
Choe, Duk-hyun [1 ]
Yoo, Sijung [1 ]
Lee, Hyun Jae [1 ]
Nam, Seung-Geol [1 ]
Jo, Sanghyun [1 ]
Park, Yoonsang [1 ]
Kim, Donghoon [1 ]
Kim, Dongmin [4 ]
Kim, Haeryong [1 ]
Shin, Keunwook [1 ]
Nahm, Sahn [2 ]
Heo, Jinseong [1 ]
机构
[1] Samsung Adv Inst Technol, Device Res Ctr DRC, Thin Film Tech Unit, Suwon 16678, South Korea
[2] Korea Univ, Sch Mat Sci Engn, Seoul 136713, South Korea
[3] Dongguk Univ, Dept Phys, Seoul 04620, South Korea
[4] Samsung Adv Inst Technol, Analyt Engn Grp Samsung Adv Inst Technol, Suwon 16678, South Korea
来源
MATERIALS TODAY NANO | 2024年 / 28卷
关键词
Ferroelectrics; Exhalative annealing; Thermal damage; Hafnia-based material; Atomic layer deposition; Low-temperature annealing; Wafer scale; HF0.5ZR0.5O2; THIN-FILMS; PHASE-TRANSITION; OXYGEN VACANCIES; DEPENDENCE; THICKNESS; BEHAVIOR; PLASMA; HFO2; ZRO2;
D O I
10.1016/j.mtnano.2024.100546
中图分类号
TB3 [工程材料学];
学科分类号
0805 ; 080502 ;
摘要
In this study, we propose a CMOS-compatible exhalative annealing (EA) method that can significantly reduce the annealing temperature of Zr-doped hafnia-based ferroelectrics (HZO). Compared to the conventional rapid thermal annealing (RTA) process, our EA process reduces the crystallization temperature ( T cryst ) of HZO films across all thickness ranges (5-10 nm). In particular, a 5 nm-thick HZO film, which is ideal for future 3D semiconductor devices, exhibited a 50 % reduction in T cryst from 500 degrees C to 250 degrees C. X-ray photoelectron spectroscopy (XPS) analysis reveals that the EA method reduces both residual carbon and oxygen vacancy concentrations. High-resolution transmission electron microscopy (HRTEM) confirmed a significant reduction in interfacial mixing between HZO and the electrodes. Capacitors made of Molybdenum (Mo) electrode/HZO/Mo electrode structure annealed using EA at 250 degrees C exhibited 2 orders of magnitude reduced leakage current at 3 MV cm- 1 , along with robust ferroelectric properties (2Pr and 2Ec values of 36.7 mu C cm-2 and 2.38 MV cm-1 , respectively). Implementing our method to ferroelectric field effect transistors (FeFETs) on a wafer scale resulted in a 33 % increase in their memory window. The CMOS-compatible EA method is effective for producing ferroelectric fieldeffect transistors on a wafer scale and is well suited for the fabrication of next-generation hafnia-based ferroelectric nonvolatile memory. EA holds great promise for developing future semiconductor devices due to its industry-friendly process and minimal thermal damage.
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页数:8
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