A Multiplier-Free Discrete Cosine Transform Architecture Using Approximate Full Adder and Subtractor

被引：2

作者：

Esmaeili, Elham ^{[1
]}

Shiri, Nabiollah ^{[1
]}

Rafiee, Mahmood ^{[1
]}

Sadeghi, Ayoub ^{[1
]}

机构：

[1] Islamic Azad Univ, Dept Elect Engn, Shiraz Branch, Shiraz 7198774731, Iran

来源：

IEEE EMBEDDED SYSTEMS LETTERS | 2024年 / 16卷 / 04期

关键词：

Discrete cosine transforms; Circuits; Adders; Image coding; Transistors; Image reconstruction; Logic gates; Approximate full adder (FA); approximate subtractor; bioimages; multiplier-free discrete cosine transform (DCT);

D O I：

10.1109/LES.2024.3395900

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new approximate full adder (FA) and a new approximate subtractor are presented, both of them have 8 transistors, and their areas are 0.1944 and 0.1689 mu m(2), respectively. The FA experiences three errors, while the subtractor shows two errors. In both circuits, to improve the speed, output swing, and drivability, the gate diffusion input (GDI) and dynamic threshold (DT) techniques are implemented by carbon nanotube field effect transistor (CNTFET) technology. The FA and subtractor in order are embedded in an 8-bit ripple carry adder (RCA) and an 8-bit subtractor, then they make a new approximate multiplier-free discrete cosine transform (DCT). The 8-point approximate DCT manipulation requires only addition and no multiplication. So, computational complexity is brought down. The DCT shows power delay product (PDP), peak signal-to-noise ratio (PSNR), and a figure of merit (FoM) of 63.61 fJ, 34.96 dB, and 2.39, respectively. The features of the presented approximate DCT confirm its application for image compression and noise removal in medical images.

引用

页码：441 / 444

页数：4

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