共 50 条
- [1] Collaborative Packet Header Parsing in NetFPGA-Based High Speed Switches IEEE Networking Letters, 2020, 2 (03): : 124 - 127
- [3] High Speed Network Intrusion Detection System Using FPGA PROCEEDINGS OF THE SECOND INTERNATIONAL CONFERENCE ON COMPUTER AND COMMUNICATION TECHNOLOGIES, IC3T 2015, VOL 1, 2016, 379 : 187 - 194
- [4] Smart Logic - Preventing Packet Loss in High Speed Network Intrusion Detection Systems INFORMATION SECURITY AND DIGITAL FORENSICS, 2010, 41 : 57 - +
- [5] Modeling protocol based packet header anomaly detector for network and host intrusion detection systems CRYPTOLOGY AND NETWORK SECURITY, 2007, 4856 : 209 - 227
- [6] A High Speed Network Intrusion Detection System Based On FPGA Circuits INTERNATIONAL JOURNAL OF COMPUTER SCIENCE AND NETWORK SECURITY, 2009, 9 (11): : 301 - 304
- [7] Study of High-Speed Processing for Network Intrusion Detection System MATERIALS AND MANUFACTURING TECHNOLOGY, PTS 1 AND 2, 2010, 129-131 : 1410 - 1414
- [8] Design of packet detection system for high-speed network environment 6TH INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATION TECHNOLOGY, VOLS 1 AND 2, PROCEEDINGS: BROADBAND CONVERGENCE NETWORK INFRASTRUCTURE, 2004, : 496 - 498
- [9] Network Packet Data Online Processing for Intrusion Detection System Proceeding of 2015 1st International Conference on Wireless and Telematics (ICWT), 2015,
- [10] One Data Preprocessing Method in High-speed Network Intrusion Detection ICWMMN 2010, PROCEEDINGS, 2010, : 60 - 63