Novel many-core architecture design for real-time image processing

被引：0
作者：
Liu, Zhentao [1 ]
Li, Tao [2 ]
Huang, Hucai [2 ]
Han, Jungang [2 ]
Shen, Xubang [1 ]
机构：
[1] School of Microelectronic, Xidian Univ., Xi'an
[2] School of Electronic Engineering, Xi'an Univ. of Posts and Telecommunications, Xi'an
来源：
Xi'an Dianzi Keji Daxue Xuebao/Journal of Xidian University | 2015年 / 42卷 / 02期
关键词：
Data-flow; Many-core; Parallel computin; Polymorphic reconfigurable architecture;
D O I：
10.3969/j.issn.1001-2400.2015.02.016
中图分类号：
学科分类号：
摘要：
Based on the data-flow model and hardware reconfigurable technology, a polymorphic reconfigurable many-core processor architecture is presented for image processing. It is a scalable hierarchically organized parallel architecture, which is capable of supporting a dynamic mixture of multiple parallel computing models, and overcomes the inefficiency of traditional data-flow implementation by using distributed shared memory and neighbor interconnect architecture with hardware handshaking. From the beginning of the architecture design, based on the VC++, the integrated simulation platform (ISE) is developed for verifying the architecture and the performance of the instruction set. In addition, we also implement the proposed architecture on the FPGA. Experimental results show that the architecture can be used in many image processing applications, and achieve the throughput close to that of the ASIC and the performance better than that of the GPU. ©, 2015, Science Press. All right reserved.
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页码：95 / 101
页数：6
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