A Noise Immune Double Suspended Gate MOSFET for Ultra Low-Power Applications

被引：0
|
作者：
Sengupta, Savio Jay [1 ]
Goswami, Bijoy [1 ]
Das, Pritam [1 ]
Sarkar, Subir Kumar [1 ]
机构：
[1] Department of ETCE, Jadavpur University, Kolkata,700032, India
来源：
Silicon | 2022年 / 14卷 / 10期
关键词：
We are highly obliged that our reputed institute Jadavpur University has provided all the facilities and infrastructure. This support and the infrastructure help us to complete the research article;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：5091 / 5101
相关论文
共 50 条
  • [11] A Low-Noise Low-Power MOSFET only Electrocardiogram Amplifier
    Ghamati, Maryam
    Maymandi-Nejad, Mohammad
    2013 21ST IRANIAN CONFERENCE ON ELECTRICAL ENGINEERING (ICEE), 2013,
  • [12] Double-gate MOSFET Model Implemented in Verilog-AMS Language for the Transient Simulation and the Configuration of Ultra Low-power Analog Circuits
    Smaani, Billel
    Meraihi, Yacin
    Nafa, Fares
    Benlatreche, Mohamed Salah
    Akroum, Hamza
    Latreche, Saida
    INTERNATIONAL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS, 2021, 67 (04) : 609 - 614
  • [13] Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits
    Roy, Nirmal Ch.
    Gupta, Abhinav
    Rai, Sanjeev
    MICROELECTRONICS JOURNAL, 2015, 46 (10) : 916 - 922
  • [14] Ultra Low-Power OTA for Biomedical Applications
    Hesari, Shahram H.
    Hedayatipour, Ava
    Aslanzadeh, Shaghayegh
    Islam, Syed K.
    2019 UNITED STATES NATIONAL COMMITTEE OF URSI NATIONAL RADIO SCIENCE MEETING (USNC-URSI NRSM), 2019,
  • [15] Double-gate SOI devices for low-power and high-performance applications
    Roy, K
    Mahmoodi, H
    Mukhopadhyay, S
    Ananthan, H
    Bansal, A
    Cakici, T
    19TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2005, : 445 - 452
  • [16] Double-gate SOI devices for low-power and high-performance applications
    Roy, K
    Mahmoodi, H
    Mukhopadhyay, S
    Ananthan, H
    Bansal, A
    Cakici, T
    ICCAD-2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, 2005, : 217 - 224
  • [17] Nanoscale Tri Gate MOSFET for Ultra Low Power Applications Using High-k Dielectrics
    Nirmal, D.
    Kumar, P. Vijay
    Joy, Doreen
    Jebalin, Binola K.
    Kumar, N. Mohan
    PROCEEDINGS OF THE 2013 IEEE 5TH INTERNATIONAL NANOELECTRONICS CONFERENCE (INEC), 2013, : 12 - 19
  • [18] Low-Power and High Speed SRAM for Ultra Low Power Applications
    Meshram, Neha
    Prasad, Govind
    Sharma, Divaker
    Mandi, Bipin Chandra
    2022 IEEE INTERNATIONAL IOT, ELECTRONICS AND MECHATRONICS CONFERENCE (IEMTRONICS), 2022, : 475 - 480
  • [19] Double gate-MOSFET subthreshold circuit for ultralow power applications
    Kim, JJ
    Roy, K
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2004, 51 (09) : 1468 - 1474
  • [20] High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model
    Kumar, Prashant
    Vashishath, Munish
    Gupta, Neeraj
    Gupta, Rashmi
    SILICON, 2022, 14 (13) : 7725 - 7734
12345