共 50 条
- [41] A new low thermal budget approach to interface nitridation for ultra-thin silicon dioxide gate dielectrics by combined plasma-assisted and rapid thermal processing CHARACTERIZATION AND METROLOGY FOR ULSI TECHNOLOGY, 1998, 449 : 273 - 277
- [42] Plasma-induced-damage (PID) free 29A nitrided gate oxide of 130nm CMOS devices for high performance microprocessor manufacturing 2000 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP FINAL REPORT, 2000, : 40 - 44
- [45] Physical and electrical properties of MOCVD and ALD deposited HfZrO4 gate dielectrics for 32nm CMOS high performance logic SOI technologies PHYSICS AND TECHNOLOGY OF HIGH-K MATERIALS 8, 2010, 33 (03): : 3 - 14
- [47] INTEGRATION OF PLASMA-ASSISTED AND RAPID THERMAL-PROCESSING FOR LOW-THERMAL BUDGET PREPARATION OF ULTRA-THIN DIELECTRICS FOR STACKED-GATE DEVICE STRUCTURES JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1994, 33 (12B): : 7061 - 7070
- [49] Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, 2005, : 511 - 514
- [50] Conformable formation of high quality ultra-thin amorphous Ta2O5 gate dielectrics utilizing water assisted deposition (WAD) for sub 50 nm damascene metal gate MOSFET INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, : 649 - 652