Investigation of ultra thin thermal nitrided gate dielectrics in comparison to plasma nitrided gate dielectrics for high-performance logic application for 65nm

被引:0
|
作者
AMD Fab36 LLC and Co. KG, Wilschdorfer Landstr. 101, 01109 Dresden, Germany [1 ]
不详 [2 ]
机构
来源
Mater Sci Forum | 2008年 / 153-163期
关键词
Alternative solutions - Comprehensive comparisons - High-performance logic applications - Nitrogen concentrations - Plasma Nitridation - Plasma nitrided gate dielectrics - Reliability characterization - Thermal nitridation;
D O I
10.4028/www.scientific.net/msf.573-574.153
中图分类号
学科分类号
摘要
In this work we present a comprehensive comparison of ultra thin thermally nitrided (TN) to plasma nitrided (PN) gate dielectrics (GD). We will show that thermal nitridation is a promising technique to increase the nitrogen concentration up to 25%. Furthermore, we will demonstrate that ultra thin thermally nitrided GD have the potential to be an alternative solution compared to plasma nitrided GD. This work includes the analysis of physical and electrical parameters as well as reliability results from reliability characterization. Additionally, we investigated the impact of Deuterium on electrical parameters and reliability behavior.
引用
收藏
相关论文
共 50 条
  • [41] A new low thermal budget approach to interface nitridation for ultra-thin silicon dioxide gate dielectrics by combined plasma-assisted and rapid thermal processing
    Niimi, H
    Yang, HY
    Lucovsky, G
    CHARACTERIZATION AND METROLOGY FOR ULSI TECHNOLOGY, 1998, 449 : 273 - 277
  • [42] Plasma-induced-damage (PID) free 29A nitrided gate oxide of 130nm CMOS devices for high performance microprocessor manufacturing
    Klein, G
    Nariman, H
    Wu, D
    Tao, J
    Bandyopadhyay, B
    Wristers, D
    Ibok, E
    McBride, M
    Tsiang, J
    Ju, DH
    2000 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP FINAL REPORT, 2000, : 40 - 44
  • [43] Application of Thermal Plasma Jet Irradiation to Crystallization and Gate Insulator Improvement for High-Performance Thin-Film Transistor Fabrication
    Higashi, Seiichiro
    Hayashi, Shohei
    Hiroshige, Yasuo
    Nishida, Yusuke
    Murakami, Hideki
    Miyazaki, Seiichi
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2011, 50 (03)
  • [44] Surface-modified high-k oxide gate dielectrics for low-voltage high-performance pentacene thin-film transistors
    Kim, Chang Su
    Jo, Sung Jin
    Lee, Sung Won
    Kim, Woo Jin
    Baik, Hong Koo
    Lee, Se Jong
    ADVANCED FUNCTIONAL MATERIALS, 2007, 17 (06) : 958 - 962
  • [45] Physical and electrical properties of MOCVD and ALD deposited HfZrO4 gate dielectrics for 32nm CMOS high performance logic SOI technologies
    Kelwing, T.
    Mutas, S.
    Trentzsch, M.
    Naumann, A.
    Trui, B.
    Herrmann, L.
    Graetsch, F.
    Klein, C.
    Wilde, L.
    Ohsiek, S.
    Weisheit, M.
    Peeva, A.
    Richter, I.
    Prinz, H.
    Wuerfel, A.
    Carter, R.
    Stephan, R.
    Kuecher, P.
    Hansch, W.
    PHYSICS AND TECHNOLOGY OF HIGH-K MATERIALS 8, 2010, 33 (03): : 3 - 14
  • [46] The performance and reliability of PMOSFET's with ultrathin silicon nitride/oxide stacked gate dielectrics with nitrided Si-SiO2 interfaces prepared by remote plasma enhanced CVD and post-deposition rapid thermal annealing
    Wu, Y
    Lucovsky, G
    Lee, YM
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2000, 47 (07) : 1361 - 1369
  • [47] INTEGRATION OF PLASMA-ASSISTED AND RAPID THERMAL-PROCESSING FOR LOW-THERMAL BUDGET PREPARATION OF ULTRA-THIN DIELECTRICS FOR STACKED-GATE DEVICE STRUCTURES
    LUCOVSKY, G
    MA, Y
    HATTANGADY, SV
    LEE, DR
    LU, Z
    MISRA, V
    WORTMAN, JJ
    JING, Z
    WHITTEN, JL
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1994, 33 (12B): : 7061 - 7070
  • [48] Parameter extraction using novel phenomena in nano-MOSFETs with ultra-thin (EOT=0.46-1.93 nm) high-K gate dielectrics
    Kar, S
    THIN SOLID FILMS, 2006, 504 (1-2) : 178 - 182
  • [49] Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths
    Singh, DV
    Sleight, JW
    Hergenrother, JM
    Ren, Z
    Jenkins, KA
    Dokumaci, O
    Black, L
    Chang, JB
    Nakayama, H
    Chidambarrao, D
    Venigalla, R
    Pan, J
    Natzle, W
    Tessier, BL
    Nomura, A
    Ott, JA
    Ieong, M
    Haensch, W
    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, 2005, : 511 - 514
  • [50] Conformable formation of high quality ultra-thin amorphous Ta2O5 gate dielectrics utilizing water assisted deposition (WAD) for sub 50 nm damascene metal gate MOSFET
    Inumiya, S
    Morozumi, Y
    Yagishita, A
    Saito, T
    Gao, DW
    Choi, D
    Hasebe, K
    Suguro, K
    Tsunashima, Y
    Arikado, T
    INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, : 649 - 652