A novel delay-locked loop structure for DDR SDRAM controller

被引：0
|
作者：
Ye, Bo [1 ]
Luo, Min [1 ]
Wang, Zishi [2 ]
机构：
[1] Bell Labs, Shanghai 201203, China
[2] ASIC and System State Key Lab, Fudan University, Shanghai 200433, China
来源：
Guti Dianzixue Yanjiu Yu Jinzhan/Research and Progress of Solid State Electronics | 2008年 / 28卷 / 02期
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页码：299 / 303
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