Multiple constant multiplication for digit-serial implementation of low power FIR filters

被引：0

作者：

Department of Electrical Engineering, Linköping University, SE-581 83 Linköping, Sweden ^{[1
]}

机构：

来源：

WSEAS Trans. Circuits Syst. | 2006年 / 7卷 / 1001-1008期

关键词：

Adders - Algorithms - Computational complexity - Digital arithmetic - Redundancy - Shift registers;

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暂无

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摘要：

Multiple constant multiplication (MCM) is an efficient way of implementing several constant multiplications with the same input data. The coefficients are expressed using shifts, adders, and subtracters. By utilizing redundancy between the coefficients the number of adders and subtracters is reduced resulting in a low complexity implementation. However, for digit-serial arithmetic a shift requires a flip-flop, and, hence, the number of shifts should be taken into consideration as well. In this work we investigate the area, speed, power trade-offs for implementation of FIR filters using MCM and digit-serial arithmetic. We also introduce an algorithm for reducing both the number of adders and subtracters as well as the number of shifts.

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