Design and implementation of an FDP chip

被引：0

作者：

Chen, Liguang ^{[1
]}

Wang, Yabin ^{[1
]}

Wu, Fang ^{[1
]}

Lai, Jinmei ^{[1
]}

Tong, Jiarong ^{[1
]}

Zhang, Huowen ^{[1
]}

Tu, Rui ^{[1
]}

Wang, Jian ^{[1
]}

Wang, Yuan ^{[1
]}

Shen, Qiushi ^{[1
]}

Yu, Hui ^{[1
]}

Huang, Junnai ^{[1
]}

Lu, Haizhou ^{[1
]}

Pan, Guanghua ^{[1
]}

机构：

[1] ASIC and System State Key Laboratory, Fudan University, Shanghai 200433, China

来源：

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors | 2008年 / 29卷 / 04期

关键词：

CMOS integrated circuits - Random access storage;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

A novel Fudan programmable logic chip (FDP) was designed and implemented with a SMIC 0.18 μm CMOS logic process. The new 3-LUT based logic cell circuit increases logic density about 11% compared with a traditional 4-input LUT. The unique hierarchy routing fabrics and effective switch box optimize the routing wire segments and make it possible for different lengths to connect directly. The FDP contains 1,600 programmable logic cells, 160 programmable I/O, and 16kbit dual port block RAM. Its die size is 6.104 mm × 6.620 mm, with the package of QFP208. The hardware and software cooperation tests indicate that FDP chip works correctly and efficiently.

引用

页码：713 / 718