Design of low-power multiplexers for FPGA

被引：0

作者：

Li, Liewen ^{[1
,2
]}

Gui, Weihua ^{[1
]}

Yang, Chunhua ^{[1
]}

Hu, Xiaolong ^{[1
]}

机构：

[1] School of Information Science and Engineering, Central South University, Changsha 410075, China

[2] Department of Electronic Information Engineering, Changsha Normal University, Changsha 410100, China

来源：

Zhongnan Daxue Xuebao (Ziran Kexue Ban)/Journal of Central South University (Science and Technology) | 2014年 / 45卷 / 05期

关键词：

Logic gates - Electric losses - Field programmable gate arrays (FPGA) - Integrated circuit design;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

Aiming at the increasingly serious power dissipation problem of field programmable gate array (FPGA) caused by their growing integration and speed, a new design method for multiplexers suitable for FPGA was proposed. Based on the phenomenon of the used multiplexers in FPGA containing many idle transistors, the proposed method reduces the leakage power dissipation of idle transistors in multiplexer by using reverse body bias technique. The simulation results show that the leakage power of multiplexers designed with the new method can be reduced by about 28.97% of that of conventionally designed multiplexers while maintaining other performance. In addition, the proposed method can reduce the leakage power dissipation of unused multiplexers in FPGA and further sharply reduce the static power of FPGA.

引用

页码：1496 / 1502