New dual-Vth assignment technique for design of low power CMOS adder

被引：0

作者：

Fakir, Kausar ^{[1
]}

Mande, Sudhakar S. ^{[2
]}

机构：

[1] Deparment of Electronics and Telecommunication Engineering, Ramrao Adik Institute of Technology, Navi Mumbai

[2] Deparment of Electronics and Telecommunication Engineering, Don Bosco Institute of Technology, Mumbai

来源：

International Journal of Power Electronics | 2024年 / 20卷 / 04期

关键词：

CMOS; dual threshold voltage; full adder; low power; PBDoE; Plackett Burman design of experiment; ripple carry adder;

D O I：

10.1504/IJPELEC.2024.142627

中图分类号：

学科分类号：

摘要：

A novel design of sensitivity-based dual threshold voltage (Vth) full adder circuit is presented in this paper. Transistors of conventional CMOS full adder circuit are assigned with dual-Vth according to the sensitivity of transistors to delay variations along all paths from every input to output terms. Plackett Burman design of experiment (PBDoE) method is applied to find out sensitivity of every transistor to delay due to variation in its threshold voltage. Transistors of conventional CMOS full adder circuit, which are not sensitive to delay are assigned with high Vth. This sensitivity-based assignment of dual-Vth will help to reduce leakage power without affecting speed of the circuit. The proposed circuit is simulated in 32 nm CMOS technology. Results shows 24% reduction in leakage power of the proposed circuit compared to conventional CMOS full adder circuit. This proposed work is extended to design dual-Vth N-bit ripple carry adder (RCA). Copyright © 2024 Inderscience Enterprises Ltd.

引用

页码：301 / 317

页数：16

共 30 条

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