Efficient LDPC Code Design based on Genetic Algorithm for IoT Systems

被引：0

作者：

Nguyen-Van, Thanh-Loc ^{[1
]}

Do-Duy, Tan ^{[1
]}

Huynh-The, Thien ^{[1
]}

机构：

[1] Department of Computer and Communication Engineering, Faculty of Electrical and Electronics Engineering, Ho Chi Minh City University of Technology and Education (HCMUTE)

来源：

EAI Endorsed Transactions on Industrial Networks and Intelligent Systems | 2024年 / 11卷 / 04期

关键词：

genetic algorithm; Internet of Things; LDPC; short block length;

D O I：

10.4108/EETINIS.V11I4.5843

中图分类号：

学科分类号：

摘要：

In this paper†, we propose a low-density parity check (LDPC) code design scheme that improves the performance of the existing genetic algorithm-based LDPC scheme. In particular, we enhance the performance of the LDPC code by removing the girth-4 property of the parity check matrix and utilizing the min-sum decoding algorithm instead of the belief propagation decoding algorithm. In addition, we consider various short block-length scenarios, specifically focusing on 64-bit and 128-bit lengths, which are well-suited for IoT systems. Then, we evaluate the block error rate (BLER) of the LDPC code over the binary input additive white Gaussian noise (BI-AWGN) channel. Finally, extensive simulation results indicate that our proposed approach achieves more than 11% gain in terms of BLER compared with the benchmarked schemes. © 2024 Nguyen-Van et al., licensed to EAI. This is an open access article distributed under the terms of the CC BY-NC-SA 4.0, which permits copying, redistributing, remixing, transformation, and building upon the material in any medium so long as the original work is properly cited.

引用

共 22 条

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