Power Hardware-in-the-Loop Emulation for SPMSM Under Fault Scenarios

This article aims to achieve the emulation of surface permanent magnet synchronous motors (SPMSMs) under various fault scenarios using power hardware-in-the-loop (PHIL) technology. Three prevalent fault models, including resistance unbalance fault (RUF), open-phase fault (OPF), and inter-turn short-circuit fault (ISCF), are formulated in this study. To ensure precise current control in the PHIL setup, the coupling-proportional-integral-resonant (CPIR) control method is proposed. This approach enhances the accuracy of tracking the second-order harmonic in the dq-axes, arising from the presence of the negative sequence current. Through the utilization of the PHIL-based motor test bench, the emulation capabilities for different fault scenarios are rigorously verified by conducting comprehensive comparisons between experimental results and theoretical results obtained through numerical analysis of various motor fault models. The experimental results demonstrate that the proposed CPIR control method improves current control accuracy under different motor fault scenarios. Particularly noteworthy is the significant reduction in the divergence index (DI) value from 44.36% to 15.69% for the OPF scenario. This rigorous verification process ensures the reliability of PHIL emulation and highlights its potential for successfully emulating SPMSM under various fault scenarios.