Low-jitter fast-locked 10.9−12.0 GHz charge-pump phase-locked loop

被引:0
|
作者
Zhan, Yongzheng [1 ]
Li, Rengang [1 ]
Li, Tuo [1 ]
Zou, Xiaofeng [1 ]
Zhou, Yulong [1 ]
Hu, Qingsheng [2 ,3 ]
Li, Lianming [3 ]
机构
[1] Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Limited Company, Jinan,250101, China
[2] Institute of RF- and OE-ICs, Southeast University, Nanjing,210096, China
[3] School of Information Science and Engineering, Southeast University, Nanjing,210096, China
关键词
Phase locked loops;
D O I
10.3785/j.issn.1008-973X.2024.11.010
中图分类号
学科分类号
摘要
引用
收藏
页码:2290 / 2298
相关论文
共 50 条
  • [41] Motivations towards BIST and DfT for embedded charge-pump phase-locked loop frequency synthesisers
    Burbidge, MJ
    Lechner, A
    Bell, G
    Richardson, AMD
    IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2004, 151 (04): : 337 - 348
  • [42] Non-linear behaviour of charge-pump phase-locked loops
    Wiegand, C.
    Hedayat, C.
    Hilleringmann, U.
    ADVANCES IN RADIO SCIENCE, 2010, 8 : 161 - 166
  • [43] A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm
    Hung, Chao-Ching
    Liu, Shen-Iuan
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2011, 58 (06) : 321 - 325
  • [44] Energy and timing characterization of VLSI charge-pump phase-locked loops
    Duarte, D
    Vijaykrishnan, N
    Irwin, MJ
    IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2003, : 341 - 344
  • [45] Structural fault diagnosis in charge-pump based phase-locked loops
    Medury, A
    Carlson, I
    Alvandpour, A
    Stensby, J
    18TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: POWER AWARE DESIGN OF VLSI SYSTEMS, 2005, : 842 - 845
  • [46] A high-performance CMOS charge-pump for phase-locked loops
    Zhou, Jianzheng
    Wang, Zhigong
    2008 INTERNATIONAL CONFERENCE ON MICROWAVE AND MILLIMETER WAVE TECHNOLOGY PROCEEDINGS, VOLS 1-4, 2008, : 839 - 842
  • [47] A low jitter and low-power phase-locked loop design
    Chen, KH
    Liao, HS
    Tzou, LJ
    ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL II: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY, 2000, : 257 - 260
  • [48] JITTER REDUCTION OF A DIGITAL PHASE-LOCKED LOOP
    YAMASHITA, M
    TSUJI, T
    NISHIMURA, T
    MURATA, M
    NAMEKAWA, T
    PROCEEDINGS OF THE IEEE, 1976, 64 (11) : 1640 - 1641
  • [49] DIGITAL PHASE-LOCKED LOOP WITH JITTER BOUNDED
    WALTERS, SM
    TROUDET, T
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1989, 36 (07): : 980 - 987
  • [50] PULL-IN CHARACTERISTICS OF PHASE-LOCKED LOOP CONSIDERING FAST JITTER
    YAMASHITA, M
    MATSUDA, Y
    MURATA, M
    NAMEKAWA, T
    ELECTRONICS & COMMUNICATIONS IN JAPAN, 1977, 60 (02): : 26 - 33