共 50 条
- [41] Motivations towards BIST and DfT for embedded charge-pump phase-locked loop frequency synthesisers IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2004, 151 (04): : 337 - 348
- [44] Energy and timing characterization of VLSI charge-pump phase-locked loops IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2003, : 341 - 344
- [45] Structural fault diagnosis in charge-pump based phase-locked loops 18TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: POWER AWARE DESIGN OF VLSI SYSTEMS, 2005, : 842 - 845
- [46] A high-performance CMOS charge-pump for phase-locked loops 2008 INTERNATIONAL CONFERENCE ON MICROWAVE AND MILLIMETER WAVE TECHNOLOGY PROCEEDINGS, VOLS 1-4, 2008, : 839 - 842
- [47] A low jitter and low-power phase-locked loop design ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL II: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY, 2000, : 257 - 260
- [48] JITTER REDUCTION OF A DIGITAL PHASE-LOCKED LOOP PROCEEDINGS OF THE IEEE, 1976, 64 (11) : 1640 - 1641
- [49] DIGITAL PHASE-LOCKED LOOP WITH JITTER BOUNDED IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1989, 36 (07): : 980 - 987
- [50] PULL-IN CHARACTERISTICS OF PHASE-LOCKED LOOP CONSIDERING FAST JITTER ELECTRONICS & COMMUNICATIONS IN JAPAN, 1977, 60 (02): : 26 - 33