Low-jitter fast-locked 10.9−12.0 GHz charge-pump phase-locked loop

被引：0

作者：

Zhan, Yongzheng ^{[1
]}

Li, Rengang ^{[1
]}

Li, Tuo ^{[1
]}

Zou, Xiaofeng ^{[1
]}

Zhou, Yulong ^{[1
]}

Hu, Qingsheng ^{[2
,3
]}

Li, Lianming ^{[3
]}

机构：

[1] Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Limited Company, Jinan

[2] Institute of RF- and OE-ICs, Southeast University, Nanjing

[3] School of Information Science and Engineering, Southeast University, Nanjing

来源：

Zhejiang Daxue Xuebao (Gongxue Ban)/Journal of Zhejiang University (Engineering Science) | 2024年 / 58卷 / 11期

关键词：

charge pump; high speed; low jitter; serial link; voltage-controlled oscillator (VCO);

D O I：

10.3785/j.issn.1008-973X.2024.11.010

中图分类号：

学科分类号：

摘要：

A low-jitter high-speed charge-pump phase-locked loop (CPPLL) suitable for high-speed SerDes serial link was designed using 65 nm CMOS technology. Loop bandwidth and circuit structure of voltage-controlled oscillator (VCO), charge pump (CP), phase frequency detector (PFD) were optimized to reduce jitter caused by voltage ripple and internal noise. CPPLL can achieve a stable clock signal with the smaller jitter offset while meeting the wide frequency range and high speed requirements of SerDes link. Chip area including the entire pads is 0.309 mm2. The measurement results show that CPPLL can generate a 10.9-12 GHz clock signal and exhibit a phase noise of -111.47 dBc/Hz and a reference spur of -25.14 dBc and a figure-of-merit (FoM) of -223.5 dB at 10 MHz offset. It takes 600 μs to generate a stable 11.3 GHz clock signal, and its RMS jitter is 973.9 fs when the reference frequency is 706.25 MHz, which is approximately 0.065 UI. The power consumption is 47.3 mW at the supply voltage of 1.2 V. The proposed phase-locked loop (PLL) is suitable for high-speed communication link systems at 20 Gb/s and above. © 2024 Zhejiang University. All rights reserved.

引用

页码：2290 / 2298

页数：8

共 30 条

[1] ROSHAN-ZAMIR A, IWAI T, FAN Y H, Et al., A 56 Gb/s PAM4 receiver with low-overhead threshold and edge-based DFE FIR and IIR-tap adaptation in 65nm CMOS, IEEE Custom Integrated Circuits Conference, pp. 1-4, (2018)
[2] SEGAL Y, LAUFER A, KHAIRI A, Et al., A 1.41 pJ/b 224 Gb/s PAM-4 SerDes receiver with 31dB loss compensation, International Solid-State Circuits Conference, pp. 114-115, (2022)
[3] POON C F, ZHANG W F, CHO J H, Et al., A 1.24-pJ/b 112-Gb/s (870 Gb/s/mm) transceiver for in-package links in 7-nm FinFET, IEEE Journal of Solid-State Circuits, 57, 4, pp. 1199-1210, (2022)
[4] LU P., A 25.6-27.5GHz phase-locked loop for SerDes transceiver clocking in 5nm FinFET, IEEE Nordic Circuits and Systems Conference, pp. 1-4, (2021)
[5] XIN Kewei, LV Fangxu, WANG Jianye, Et al., A 12.5 GHz clock generator applicable for 4-way 100 Gbps high-speed serial interface circuits, Journal of Air Force Engineering University: Natural Science Edition, 20, 5, pp. 64-69, (2019)
[6] LI Peijie, SHEN Jianliang, YUAN Hongxiao, Et al., A multi-protocol SerDes circuit for the application in software defined interconnection system, ACTA Electronica Sinica, 49, 4, pp. 817-823, (2021)
[7] SAURABH K, KUMAR S Y., A low-phase-noise self-aligned sub-harmonically injection-locked PLL using aperture phase detector-based DLL windowing technique, IEEE Access, 11, pp. 6641-6655, (2023)
[8] YANG X, LIU F, HUO Z L., Wide-range and high-accuracy four-phase DLL with the adaptive-bandwidth scheme, Xi'an Dianzi Keji Daxue Xuebao/Journal of Xidian University, 49, 1, pp. 194-201, (2022)
[9] BAE W., State-of-the-art circuit techniques for low-jitter phase-locked loops: advanced performance benchmark FOM based on an extensive survey, IEEE International Symposium on Circuits and Systems, pp. 1-5, (2021)
[10] LIU H L, SUN Z, HUANG H Y, Et al., A 265-mu W fractional-N digital PLL with seamless automatic switching sub-sampling/sampling feedback path and duty-cycled frequency-locked loop in 65-nm CMOS, IEEE Journal of Solid-State Circuits, 54, 12, pp. 256-257, (2019)

← 1 2 3 →