A 25-32-GHz Frequency Doubler With 21% Efficiency and 41-dBc Fundamental Rejection

被引：0
|
作者：
Sun, Yu [1 ]
Li, Kai [1 ]
Yang, Geliang [2 ]
Zhang, Hao [3 ]
Ma, Kaixue [1 ]
Wang, Keping [1 ]
机构：
[1] Tianjin Univ, Sch Microelect, Tianjin 300072, Peoples R China
[2] China Elect Technol Grp Corp, Res Inst 54, Shijiazhuang 050081, Peoples R China
[3] Nanjing Res Inst Elect Technol, Nanjing 210096, Peoples R China
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2024年 / 71卷 / 10期
基金：
中国国家自然科学基金;
关键词：
Frequency doubler; millimeter wave; fundamental rejection; efficiency; SiGe; BAND; GAIN; DB;
D O I：
10.1109/TCSII.2024.3397009
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This brief presents a frequency doubler operating in the 25-32 GHz range with high fundamental rejection in the 130 nm SiGe BiCMOS process. The inductor connected to the base of common emitter transistor contributes to the harmonic reflector and input impedance matching. The output multi-frequency filter network (OMFN) suppresses the fundamental and the fourth harmonic. The measured results show that the frequency doubler achieves 3-dB gain bandwidth of 7 GHz (25-32 GHz). At an input power of 0 dBm, the proposed frequency doubler exhibits a fundamental rejection of 41 dBc and a DC power consumption of 22 mW. The second harmonic peak PAE is 20% and the peak eta is 21%. The doubler occupied an area of 0.52 mm(2) including all test pads.
引用
收藏
页码：4417 / 4421
页数：5
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