共 81 条
- [1] Xue C.-X., Et al., 16.1 A 22nm 4Mb 8b-precision ReRAM computingin-memory macro with 11.91 to 195.7TOPS/W for tiny AI edge devices, Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 245-247, (2021)
- [2] Xue C.-X., Et al., A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices, Nat. Electron., 4, pp. 81-90, (2021)
- [3] Hu M., Et al., Dot-product engine for neuromorphic computing: Programming 1T1M crossbar to accelerate matrix-vector multiplication, Proc. 53nd ACM/EDAC/IEEE Design Autom. Conf. (DAC), pp. 1-6, (2016)
- [4] Wang Z., Et al., An all-weights-on-chip DNN accelerator in 22nm ULL featuring 24×1 Mb eRRAM, Proc. IEEE Symp. VLSI Circuits, pp. 1-2, (2020)
- [5] Yoon J.-H., Chang M., Khwa W.-S., Chih Y.-D., Chang M.-F., Raychowdhury A., 29.1 A 40nm 64Kb 56.67TOPS/W readdisturb-tolerant compute-in-memory/digital RRAM macro with activefeedback-based read and in-situ write verification, Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 404-406, (2021)
- [6] Shafiee A., Et al., ISAAC: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars, Proc. ACM/IEEE 43rd Annu. Int. Symp. Comput. Architect. (ISCA), pp. 14-26, (2016)
- [7] Eryilmaz S.B., Kuzum D., Yu S., Wong H.S.P., Device and system level design considerations for analog-non-volatilememory based neuromorphic architectures, IEEE IEDM Tech. Dig., (2015)
- [8] Yu S., Et al., Binary neural network with 16 Mb RRAM macro chip for classification and online training, Proc. IEEE Int. Electron Devices Meeting (IEDM), pp. 1621-1624, (2016)
- [9] Bocquet M., Et al., In-memory and error-immune differential RRAM implementation of binarized deep neural networks, IEEE IEDM Tech. Dig., (2018)
- [10] Adam G.C., Hoskins B.D., Prezioso M., Merrikh-Bayat F., Chakrabarti B., Strukov D.B., 3-D memristor crossbars for analog and neuromorphic computing applications, IEEE Trans. Electron Devices, 64, 1, pp. 312-318, (2017)