共 50 条
- [1] Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Networks 2018 ACM/IEEE 45TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA), 2018, : 764 - 775
- [2] An improved architecture for bit-level matrix multiplication PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS I-V, 2000, : 2257 - 2264
- [3] AN IMPROVED BIT-LEVEL SYSTOLIC ARCHITECTURE FOR IIR FILTERING SYSTOLIC ARRAY PROCESSORS, 1989, : 205 - 214
- [5] Bit-level pipelined VLSI architecture for running order algorithm IEEE Trans Signal Process, 8 (2140-2144):
- [6] A dataflow architecture with distributed control for DNN acceleration 2024 13TH MEDITERRANEAN CONFERENCE ON EMBEDDED COMPUTING, MECO 2024, 2024, : 71 - 74
- [7] Mathematical modelling of Bit-Level Architecture using Reciprocal Quantum Logic PROCEEDINGS OF THE 10TH NATIONAL CONFERENCE ON MATHEMATICAL TECHNIQUES AND ITS APPLICATIONS (NCMTA 18), 2018, 1000
- [8] Bit-Level Taint Analysis 2014 14TH IEEE INTERNATIONAL WORKING CONFERENCE ON SOURCE CODE ANALYSIS AND MANIPULATION (SCAM 2014), 2014, : 255 - 264
- [9] Towards CIM-friendly and Energy-Efficient DNN Accelerator via Bit-level Sparsity PROCEEDINGS OF THE 2022 IFIP/IEEE 30TH INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC), 2022,