The Design of a 10 Bit 20 MSPS SAR ADC of the Readout Chip for GEM-TPC Detector

被引：0

作者：

Sun, Zhikun ^{[1
,2
,3
]}

Qian, Yi ^{[1
,2
,3
]}

Yang, Mingyu ^{[1
,3
]}

She, Qianshun ^{[1
,2
,3
]}

Zhao, Hongyun ^{[1
,2
,3
]}

Pu, Tianlei ^{[1
,2
,3
]}

Lu, Weijian ^{[1
,3
]}

Liu, Zhengqiang ^{[1
,3
]}

Zhang, Jiarui ^{[1
,3
]}

机构：

[1] Institute of Modern Physics, Chinese Academy of Sciences, Lanzhou

[2] Advanced Energy Science and Technology Guangdong Laboratory, Huizhou

[3] School of Nuclear Science and Technology, University of Chinese Academy of Sciences, Beijing

来源：

Dianzi Keji Daxue Xuebao/Journal of the University of Electronic Science and Technology of China | 2024年 / 53卷 / 04期

关键词：

ASIC; asynchronous SAR logic; bootstrapped switch; dynamic comparator; GEM-TPC; SAR ADC;

D O I：

10.12178/1001-0548.2023204

中图分类号：

学科分类号：

摘要：

With the continuous development of large-area gas electron multiplier-time projection chamber detectors, the density and integration of readout electronics are increasingly required. In this paper, a 10 bit, 20 MSPS successive approximation register analog-to-digital converter prototype chip is designed and fabricated by 180 nm CMOS process. Combining the SAR ADC chip with an analog front-end module and a digital signals processor, a fully digital front-end readout application specific integrated circuit for GEM-TPC is realized. The ADC is mainly composed of the DAC module, the dynamic comparator module, the asynchronous clock generation module and the SAR logic module. Simulation results show that when the input signal frequency is 1.836 MHz, the effective number of bits is 8.61 bit, and the core power consumption is about 3.3 mW/Ch. © 2024 University of Electronic Science and Technology of China. All rights reserved.

引用

页码：481 / 486

页数：5

共 15 条

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