The FinFET effect in lateral 4H-SiC and Silicon multi-gate MOSFETs

This paper presents a comprehensive investigation on the role and manifestation of the FinFET effect in low voltage 4H-SiC MOSFETs as compared to their Si counterparts. For this purpose, a finite element model of a fabricated SiC FinFET with a fin width of 55 nm is constructed and calibrated to experimental data at a range of operating temperatures. The resulting TCAD model is then applied to examine the impact of the FinFET effect on the threshold voltage and the spatial variation of the carrier density and the drift mobility in the channel for a range of doping concentrations N-A of the p-well. It is thereby shown that by reducing the fin width W-fin from conventional values greater than or similar to 500 nm down to an interval of optimal values similar to 40 nm (keeping everything else constant), it is possible to enhance the channel mobility similar to 2.5 times. This improvement is not only found to be much larger than the one predicted in Si (where it is similar to 15% according to the TCAD model) but also arises at a larger fin width (for a given N-A). In this respect, it is demonstrated that this optimal range of fin widths can be moved to even larger, more practical values by reducing the doping of the p-well. As an alternative, the on-state performance of the gate-all-around FET is also examined in detail following a similar procedure. It is hence shown that this structure can display the FinFET effect at an even larger, nearly conventional W-fin of similar to 250 nm, whilst attaining a higher channel mobility and inversion layer density even than a stripe FinFET operated at the same overdrive. Thus, in light of all these advantages, the FinFET topology can play a key role in reducing the channel resistance of SiC power MOSFETs.