A 1.25-GS/s14-bit pipelined ADC using a current-feedback flipped input buffer and large dither technique to achieve high linearity

This paper presents a 1.25-GS/s 14-bit pipelined analog-to-digital converter that employs two linearity improvement schemes. A current-feedback flipped input buffer is proposed, which can effectively mitigate the effect of non-linear parasitic capacitances, sampling circuits, and finite output impedance of tail current sources on linearity. Additionally, most of the non-linearity in the ADC core is improved by implementing the large dither injection. The proposed input buffer is designed in a 40-nm CMOS process under a 2.5-V supply voltage. The simulation results show the input buffer can achieve SFDR > 80.1 dBc and SNDR > 70 dB with a power consumption of 65 mW at 1.25-GS/s for input signal frequencies less than 1.5-GHz. The SFDR of this ADC can be improved by about 3.5 dB by using large dither technique. The entire 14-bit ADC achieves a 65.6 dB SNDR and a 78.1 dBc SFDR at 1.25-GSps while the core of ADC consumes 510 mW, achieving a FoM(w) of 262.8 fJ/conversion-step.