Design of a hardware compression encoder with a high throughput

被引：0
|
作者：
Wu C. [1 ]
Zhang W. [1 ]
Hao Y. [1 ]
机构：
[1] School of Microelectronics, Tianjin University, Tianjin
来源：
Xi'an Dianzi Keji Daxue Xuebao/Journal of Xidian University | 2022年 / 49卷 / 04期
关键词：
image compression; parallel processing; throughput; very large scale integration;
D O I：
10.19665/j.issn1001-2400.2022.04.020
中图分类号：
学科分类号：
摘要：
Aiming at the pressure of storage and transmission bandwidth massive image data in practical applications,a high throughput image compression encoder compatible with processing 8~16 bits grayscale images is designed,and the corresponding VLSI architecture is given.By analyzing the characteristics of the 16-bit gray image pixel value,and the difference between Discrete Wavelet Transform(DWT) and Optimized Truncated Embedded Module(EBCOT) with the hardware implementation of the JPEG2000 compression encoder in the processing time,the optimal parallel-series-parallel structure is proposed,and the architecture is designed with high 8-bit and low 8-bit processing,which can be processed independently or together.This architecture increases the flexibility of the encoder and greatly improves the throughput of the compression encoder.Finally,the encoder is implemented on Xilinx XC7K480T.The highest operating frequency of the encoder is 147.734 MHz,and the maximum throughput rate of the 8-bit grayscale image is 169.55 MB/s.The maximum throughput of the 16-bit grayscale image is 266.87 MB/s.Compared with existing similar encoders,the throughput is increased by more than 40%.In practical engineering applications,the encoder has not only a high reliability and good flexibility,but also a strong scalability.By controlling the parallelism,it can realize high magnification,high quality and fast compression of images with different resolutions,which is of important practical value. © 2022 Science Press. All rights reserved.
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页码：176 / 183
页数：7
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