Promoting Frequency Method for Our Own High Performance Processor Physical Design

被引：0

作者：

He, Xiaowei ^{[1
]}

Yue, Daheng ^{[1
]}

Guo, Wei ^{[1
]}

Sui, Bingcai ^{[1
]}

Deng, Quan ^{[1
]}

机构：

[1] College of Computer Science and Technology, National University of Defense Technology, Changsha 410073）（Key Laboratory of Advanced Microprocessor Chips and Systems (National University of Defense Technology), Changsha 410073

来源：

Jisuanji Yanjiu yu Fazhan/Computer Research and Development | 2024年 / 61卷 / 06期

关键词：

co-optimization; frequency; physical design; place and route; signoff;

D O I：

10.7544/issn1000-1239.202330942

中图分类号：

TN3 [半导体技术]; TN4 [微电子学、集成电路（IC）];

学科分类号：

0805 ; 080501 ; 080502 ; 080903 ; 1401 ;

摘要：

Promoting core’s frequency is the key method for increasing performance of processor. It is hard to achieve high frequency for processor core by traditional physical design flow. Based on main place and route tools, with the same process, comparable implementation area and power consumption, our own processor core frequency can be promoted by about 30% compared with original design at signoff stage, by employing manually written block netlist, logic and physical design co-optimization, custom routing rule optimization and physical design methodology adjustment. © 2024 Science Press. All rights reserved.

引用

页码：1429 / 1435

页数：6

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