A Digital SRAM-Based Computing-in-Memory Macro Supporting Parallel Maintaining for Network Management

被引：0
|
作者：
Li, Geng [1 ]
Zheng, Hanqing [1 ]
Sun, Jiacong [1 ]
Jiao, Hailong [1 ]
机构：
[1] Peking Univ, Sch Elect & Comp Engn, Shenzhen Grad Sch, Guangdong Prov Key Lab Inmemory Comp Chips, Shenzhen 518055, Peoples R China
来源：
IEEE SOLID-STATE CIRCUITS LETTERS | 2024年 / 7卷
基金：
中国国家自然科学基金;
关键词：
Random access memory; Latches; In-memory computing; Reflective binary codes; Main-secondary; Throughput; Telemetry; Queueing analysis; Encoding; Common Information Model (computing); Computing-in-memory (CIM); daisy-chain circuit (DCC); gray code; parallel maintaining; statistics counter;
D O I：
10.1109/LSSC.2024.3477619
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A digital SRAM-based computing-in-memory (CIM) macro is proposed to enable parallel maintaining for statistics counters in network management. A new 18-transistor bit-cell is designed to support in-situ counter maintaining. A joint coding scheme and a daisy-chain circuit are leveraged to enhance the throughput as well as reduce the computing energy consumption and area. The proposed CIM macro saves 6.9 x in energy at 1.2 V and 2.33 x in area compared with the conventional statistics counters in a 55-nm CMOS technology.
引用
收藏
页码：327 / 330
页数：4
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