共 50 条
- [21] Buried Power Rail Integration for CMOS Scaling beyond the 3 nm Node ADVANCED ETCH TECHNOLOGY AND PROCESS INTEGRATION FOR NANOPATTERNING XI, 2022, 12056
- [23] Physical limitations in scaling field-effect transistors and technologies beyond CMOS PHYSICS OF SEMICONDUCTOR DEVICES, VOLS 1 AND 2, 1998, 3316 : 986 - 993
- [25] Density scaling beyond the FinFET: Architecture Considerations for Gate-all-around CMOS 2016 74TH ANNUAL DEVICE RESEARCH CONFERENCE (DRC), 2016,
- [28] Scenarios of CMOS scaling 1998 5TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY PROCEEDINGS, 1998, : 12 - 16