共 50 条
- [1] Memory Partitioning for Multidimensional Arrays in High-level Synthesis 2013 50TH ACM / EDAC / IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2013,
- [3] A thread partitioning algorithm in low power high-level synthesis ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2004, : 74 - 79
- [4] Array Partitioning Method for Streaming Dataflow Optimization in High-level Synthesis 2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024, 2024, : 278 - 282
- [5] Memory Partitioning-Based Modulo Scheduling for High-level Synthesis 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2017, : 2671 - 2674
- [7] An integrated algorithm for memory allocation and assignment in high-level synthesis 39TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2002, 2002, : 608 - 611
- [8] ASAP: Automatic Sizing and Partitioning for Dynamic Memory Heaps in High-Level Synthesis 2019 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (ICFPT 2019), 2019, : 275 - 278
- [9] Fast Mapping-Based High-Level Synthesis of Pipelined Circuits PROCEEDINGS OF THE 2019 20TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), 2019, : 33 - 38
- [10] Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis FPGA'17: PROCEEDINGS OF THE 2017 ACM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE GATE ARRAYS, 2017, : 290 - 290