Low power sleepy keeper technique based VLSI architecture of Viterbi decoder in WLANs

.Wireless communication technologies have advanced from cellular networks to satellite systems which create an advancing demand for low power battery operated decoding unit.  Widely used error correction technique in the wireless communication systems is the channel coding.  In channel coding, convolutional codes are commonly used for the transmission of data over a noisy channel. The methodologies adopted in the proposed design to achieve low power and increase in performance is by designing the architecture of the Viterbi decoder at circuit level design using a sleepy keeper technique, which curtails the leakage power dissipation. The second method is by including the modified register exchange algorithm, which reduces the occurrence of error probability with low power in signal transmission in the wireless domain. Simulation of the design is executed in 45nm TSMC in Tanner-SPICE. Promising results are obtained with reduction in power 31.54% with the CMOS technology for the WLAN frequency of 2.5MHz. BER performance of the design also found to be low in the channel environment. . ©, Engineers Australia.