Effect of all-digital full-hardware process on magnetic encoder-to-digital converters

被引:0
作者
机构
[1] Liu, Ya-Jing
[2] Fan, Yu
来源
Liu, Y.-J. | 1600年 / Editorial Department of Electric Machines and Control卷 / 17期
关键词
D O I
暂无
中图分类号
学科分类号
摘要
18
引用
收藏
相关论文
共 50 条
[21]   An All-Digital Temperature Sensor with Process and Voltage Variation Tolerance for IoT Applications [J].
Chung, Ching-Che ;
Huang, Hsin-Han .
32ND IEEE INTERNATIONAL SYSTEM ON CHIP CONFERENCE (IEEE SOCC 2019), 2019, :109-112
[22]   OpenSerDes: An Open Source Process-Portable All-Digital Serial Link [J].
Kumar, Gaurav K. ;
Chatterjee, Baibhab ;
Sen, Shreyas .
PROCEEDINGS OF THE 2021 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2021), 2021, :386-391
[23]   Note: All-digital CMOS MOS-capacitor-based pulse-shrinking mechanism suitable for time-to-digital converters [J].
Chen, Chun-Chi ;
Hwang, Chorng-Sii ;
Lin, You-Ting ;
Liu, Keng-Chih .
REVIEW OF SCIENTIFIC INSTRUMENTS, 2015, 86 (12)
[24]   An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters [J].
Ta, Van-Thanh ;
Hoang, Van-Phuc ;
Pham, Van-Phu ;
Pham, Cong-Kha .
ELECTRONICS, 2020, 9 (01)
[25]   All-Digital Self-Interference Cancellation in Zero-IF Full-Duplex Transceivers [J].
Lu Tian ;
Shuai Wang ;
Zhiheng Cheng ;
Xiangyuan Bu .
中国通信, 2016, 13 (11) :27-34
[26]   Time-Mode All-Digital Delta-Sigma Time-to-Digital Converter with Process Uncertainty Calibration [J].
Yuan, Fei ;
Parekh, Parth .
2019 IEEE 62ND INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2019, :489-492
[27]   All-Digital Self-Interference Cancellation in Zero-IF Full-Duplex Transceivers [J].
Tian, Lu ;
Wang, Shuai ;
Cheng, Zhiheng ;
Bu, Xiangyuan .
CHINA COMMUNICATIONS, 2016, 13 (11) :27-34
[28]   The design of an all-digital phase-locked loop with small DCO hardware and fast phase lock [J].
Chiang, JS ;
Chen, KY .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 1999, 46 (07) :945-950
[29]   Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration [J].
Tzeng, Chao-Wen ;
Huang, Shi-Yu ;
Chao, Pei-Ying .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2014, 22 (03) :621-630
[30]   Process Variation Tolerant All-Digital Multiphase DLL for DDR3 Interface [J].
Kang, H. C. ;
Ryu, K. H. ;
Lee, D. H. ;
Lee, W. ;
Kim, S. H. ;
Choi, J. R. ;
Jung, S. O. .
IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010, 2010,