An ultra-low power SAR ADC with voltage window technique

被引：0

作者：

Wang Z.-F. ^{[1
]}

Ning N. ^{[1
]}

Wu S.-Y. ^{[1
]}

Du L. ^{[1
]}

Jiang M. ^{[1
]}

Yan X.-Y. ^{[1
]}

Wang W. ^{[1
]}

机构：

[1] State Key Lab. of Electronic Thin Film and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, 610054, Sichuan

来源：

Ning, Ning (ning_ning@uestc.edu.cn) | 1600年 / Chinese Institute of Electronics卷 / 44期

关键词：

Analog-to-digital converter (ADC); Successive approximation register (SAR); Ultra-low power; Voltage window;

D O I：

10.3969/j.issn.0372-2112.2016.01.031

中图分类号：

学科分类号：

摘要：

An ultra-low power successive approximation register analog-to-digital converter for biomedical application is proposed. Many ultra-low power design methods are utilized for its main modules. The digital-to-analog converter (DAC) employs a vcm-based and split capacitor array structure to cut down the total capacitance, so as the power consumption. Voltage window technique is used to decrease the power consumption of the comparator without sacrificing its accuracy. Furthermore, stack forcing and multi-Vt design approaches are used to reduce the leakage current under low frequency. The proposed SAR ADC is designed and simulated in 55 nm process. With 0.6 V power supply and 10 kS/s sampling rate, the ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 73.3 dB. The total power consumption is 432 nW and the figure-of-merit (FOM) is 11.4 fJ/Conv. © 2016, Chinese Institute of Electronics. All right reserved.

引用

页码：211 / 215

页数：4

共 16 条

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